Daniel Mangum
How AI on Microcontrollers Actually Works: Registering Operators
How AI on Microcontrollers Actually Works: The Computation Graph
How AI on Microcontrollers Actually Works: Operators and Kernels
Just Barely Fitting a Full Wi-Fi Stack on the nRF9151
Accessing the Qualcomm Modem over USB on the RAK5010
VPR: Arm and RISC-V Inter-Processor Communication
VPR: Nordic's First RISC-V Processor
USB UART on the Thingy:91 X
This Website is Hosted on Bluesky
USB On-The-Go on the ESP32-S3
Is It Better to Fail Spectacularly?
The Taxonomy of Hardware Security Mechanisms
Founder Mode for Non-Founders
Static Allocation in External RAM on ESP32
Wireframes are Cheap, Engineering Should Be Too
The Most Important Skill in Startup Engineering Leadership
RISC-V Bytes: Accessing the Pinecil UART with picoprobe
RISC-V Bytes: Soldering the Pinecil Breakout Board
Reflections on Running 3,000 Miles in 2023
Understanding Every Byte in a WASM Module
Zero to WASI with Clang 17
Supercon 2023 Day 3: badgecase.io
Supercon 2023 Day 2: Talks Begin, Hacking Continues
Supercon 2023 Day 1: Hello Badge
Setting Up Verible for Verilog with Neovim
A Particularly Gnarly Case of Go’s Non-Nil Interfaces
How LUTs Are Used as Storage Elements on an FPGA
The Value of Livestreaming Long-Term Projects
When Does Vivado Infer BRAM?
Microprocessors Are Tiny, But They Can’t Fit in Your Head
A Brief Retrospective on SPARC Register Windows
How To Dissect a Critical HackerNews Comment
A Single-Cycle 64-Bit RISC-V Register File
Single-Cycle and Multicycle Do Not Describe Processor Performance
Why Create a New Instruction Set Architecture?
A Three Year Bet on Chip Design
RISC-V Bytes: Semihosting with Zephyr on an ESP32
RISC-V Bytes: Zephyr Before Main
RISC-V Bytes: Zephyr on the ESP32
RISC-V Bytes: Exploring a Custom ESP32 Bootloader
Do you want to take a leap of faith?
Where does the kubelet mount volumes?
K8s ASA: Watching and Caching
K8s ASA: The Storage Interface
Welcome to Kubernetes API Server Adventures
RISC-V Bytes: Timer Interrupts
I'm on Mastodon
RISC-V Bytes: Go 1.19's Register-Based Calling Convention
RISC-V Bytes: Stack Use After Return in C, Go, and Rust
Dynamically Linked Programs with Binfmt_misc
Sandbox Programmers
Opening a UDP Socket in RISC-V Assembly
Graceful Shutdown of Responsibilities in a Growing Organization
The Missing Kubernetes Type System
RISC-V Bytes: Rust Cross-Compilation
Load-Reserved/Store-Conditional Release & Acquire Semantics
RVWMO Preserved Program Order Rule 2
RVWMO Preserved Program Order Rule 1
RISC-V Weak Memory Ordering
The Zmmul Extension
Instruction-Address-Misaligned Exceptions
Fine-Grained Address-Translation Cache Invalidation (Svinval)
NAPOT Translation Continuity (Svnapot)
Page-Based Memory Types (Svpbmt)
Memory Ordering Instructions: FENCE.I
Memory Ordering Instructions: FENCE
RISC-V Bytes: Privilege Levels
Non-Maskable Interrupts
CSR Clear and Set Bits Instructions
4-Byte Aligned Trap Vectors
ld Default Entry Point
Pipelined Trap Precision
SiFive P650
Instruction Format Regularity
Atomicity PMAs
Physical Memory Attributes (PMAs)
Access and Privilege in CSR Addresses
OpenTitan Assembly Style Guide
xv6 Teaching Operating System
Interrupt Controllers
The Hypervisor Extension
Open Hardware for the Open Cloud
Supervisor Trap Base Address Register
Supervisor Memory Management Fence Instruction
Sv32 Megapages
Sv32 Two-Level Address Translation
SUM bit in Supervisor Status Register
Sv32 Page Table Entry Permissions
Virtual Memory Addressing Modes
PMP Addressing: Top of Range
PMP and Virtual Memory
PMP Addressing: Naturally Aligned Powers of Two
Physical Memory Protection Address Matching Modes
Physical Memory Protection
Machine Exception Delegation Register
Identifying Debug Triggers
Debug Spec Architecture
Exceptions, Interrupts, and Traps
GNU Assembler RISC-V Directives
Golang Compare and Swap Usage
How Kubernetes Validates Custom Resources
Loading an Address into a CSR
View All Harts in GDB and mhartid
Machine and Supervisor Cause CSRs
Infrastructure in Your Software Packages
Supervisor Previous Privilege
HPM: Hardware Performance Monitoring
Supervisor Address Translation and Protection
Three Main Privilege Levels
CSR Field Behaviors
HSM means Hart State Management
Specifying BIOS in QEMU with OpenSBI
Viewing Registers in GDB
RISC-V Bytes: Introduction to Instruction Formats
Announcing the Research Triangle RISC-V Community Group
RISC-V Bytes: Passing on the Stack
Stepping Away from Upstream Kubernetes
RISC-V Bytes: Caller and Callee Saved Registers
RISC-V Bytes: Cross-Platform Debugging with QEMU and GDB
Using a ConfigMap as an OCI Image Cache
chdir to cwd: permission denied
Is Crossplane the Infrastructure LLVM?
Scraping controller-runtime Prometheus Metrics Locally
Rate Limiting in controller-runtime and client-go
Conference Talk: Building an Enterprise Infrastructure Control Plane on Kubernetes
Installing Vivado 2020.x on Ubuntu 20.04
Tweet Thread: Crossplane Packages and K8s Features You Thought You Didn't Have
Understanding Non-Local Jumps (setjmp/longjmp) in RISC-V Assembly
Podcast Guest: Using Kubernetes And Crossplane To Provision Cloud Infrastructure (Full Stack Journey)
Uppercase .S vs Lowercase .s File Extensions in GAS Syntax Assembly
Podcast Guest: What is Rapid Prototyping? (The DroidDevCast)
Podcast Guest: Daniel Mangum on Crossplane, building a PaaS, and Multi-Cluster Kubernetes (LOTE)
Guest Post: Adding Managed Services to Serverless with Crossplane and OpenFaaS (OpenFaaS Blog)
Guest Post: Connecting AWS managed services to your Argo CD pipeline with open source Crossplane (AWS Open Source Blog)
Podcast Guest: Gerhard goes to KubeCon (part 2) (The Changelog)
Please Mind Your Metaphors
HashiCode Ep. 1: Terraform Remote State Backend Locking
Introducing HashiCode
Presence vs. Planning
Understanding ETL to ELT by Going to Costco
Immediate Reflections on the AWS Solutions Architect Associate Exam (February 2019)
Why You Shouldn't Use ^Parameters with CloudFormation Templates
Dockerfile for Building Ionic Apps
Simple Linux Command Line Using Docker
Local Kong API Gateway for Go Web Server
Why I am Starting a Blog
About Me